1. Field of the Invention
The present invention generally relates to methods and systems for image based specimen process control.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on specimens to drive higher yield in the manufacturing process and thus higher profits. Inspection has always been an important part of fabricating semiconductor devices. However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devices because smaller defects can cause the devices to fail.
Defect review typically involves re-detecting defects detected as such by an inspection process and generating additional information about the defects at a higher resolution using either a high magnification optical system or a scanning electron microscope (SEM). Defect review is therefore performed at discrete locations on specimens where defects have been detected by inspection. The higher resolution data for the defects generated by defect review is more suitable for determining attributes of the defects such as profile, roughness, more accurate size information, etc.
Metrology processes are also used at various steps during a semiconductor manufacturing process to monitor and control the process. Metrology processes are different than inspection processes in that, unlike inspection processes in which defects are detected on specimens, metrology processes are used to measure one or more characteristics of the specimens that cannot be determined using currently used inspection tools. For example, metrology processes are used to measure one or more characteristics of specimens such as a dimension (e.g., line width, thickness, etc.) of features formed on the specimens during a process such that the performance of the process can be determined from the one or more characteristics. In addition, if the one or more characteristics of the specimens are unacceptable (e.g., out of a predetermined range for the characteristic(s)), the measurements of the one or more characteristics of the specimens may be used to alter one or more parameters of the process such that additional specimens manufactured by the process have acceptable characteristic(s).
Metrology processes are also different than defect review processes in that, unlike defect review processes in which defects that are detected by inspection are re-visited in defect review, metrology processes may be performed at locations at which no defect has been detected. In other words, unlike defect review, the locations at which a metrology process is performed on specimens may be independent of the results of an inspection process performed on the specimens. In particular, the locations at which a metrology process is performed may be selected independently of inspection results.
Currently, process control and yield analysis is performed using inline inspection and metrology such as that described above. Defects may be defined mainly by using one or more inspection parameters above a certain threshold. In other words, events from defect inspection must be above a certain threshold to be reported as defects. In most cases, these reported events are being used to identify locations on wafers as defective. For example, a gray level difference of 31 would be reported as a defect if the threshold for gray level difference is set to 30. These defects are then used to classify and identify potential mode failures in processes or tools. Defects can then be classified and used for isolating problems in semiconductor manufacturing. However, the definition of defect thresholds is limited to values set based on operating parameters within the inspection.
Due to the subtlety in manifestation of pattern deformation or random defects, some marginal events that are critical to device performance may be hidden in the data and never be detected as defects. Subtle defects or deformation in patterns may be binned as nuisance or non-critical defects. In addition, for advanced designs with tighter geometry and smaller process window, some critical defects can be undetected using traditional defect thresholds. Certain characteristics (which may be described as a combination of many optical attributes) in printed images may impact device performance but it is difficult to define a threshold to detect them as defects. Certain subtle failure modes can only be identified by extracting multiple attributes from inspection images (optical or SEM) and performing analysis such as data mining or advanced correlation techniques.
Such definitions of defects also depend upon the response variables (such as parametric test data or functional test) and at the time of defect reporting, it is not practical to use image characteristics as metrics to define defects. For example, critical defects may be defined by visual failure such as open, short, pattern deformation, size of defect etc. and correlation to electrical test such as parametric or functional tests or failure analysis. One of the key limitations in the currently used methods is that inspection data has to be binned (e.g., sizing) or classified (shapes, nuisance, real, etc.) before being used for device characterization and yield improvement work and therefore uses mostly supervised approaches. Inspection images (both optical and SEM images) contain a lot of information that is not being fully utilized for device characterization and yield learning.
Some currently available systems are configured to acquire images for post processing applications. For example, some currently used systems are configured for acquiring image patches associated with defects in wafer inspection lot results. The image acquisition only provides image patches of the locations in which one or more defects are detected. Such image acquisition also does not have the capability to acquire arbitrary images of interest that greatly limits the usefulness of the image post-processing applications. Some other currently used systems are configured for acquiring image patches from electron beam review results. Such image acquisition only provides limited data samples due to relatively low wafer coverage in electron beam review. Some image acquisition may be performed using entire swaths of image data stored in a storage medium. Such image acquisition may capture whole swath images that provide the maximum information for the post processing applications. However, this method can only provide limited image data sets due to the extremely large data size (e.g., 40 TB of data per full wafer scan at nominal inspection pixel size on some currently used inspection tools). This practical constraint limits the usefulness of the post processing applications. In addition, there is no existing computing infrastructure to enable the image post processing applications using the above acquired images as well as associated data from multiple data sources at once.
Accordingly, it would be advantageous to develop systems and methods for detecting anomalies in images of a specimen that do not have one or more of the disadvantages described above.